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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
FEATURES
* 2 differential LVDS bank outputs * 2 differential LVPECL clock input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: 3.2GHz * Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input * Output skew: TBD * Part-to-part skew: TBD * Propagation delay: 280ps (typical) * 3.3V supply voltage * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS854210 is a low skew, high performance dual 1-to-5 Differential-to-LVDS Fanout HiPerClockSTM Buffer and a member of the HiPerClockS TM family of High Perfor mance Clock Solutions from ICS. The ICS854210 is characterized to operate from a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS854210 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
PCLKA nPCLKA QA0 nQA0 QA1 nQA1 QA2 nQA2 QA3 nQA3 QA4 nQA4
PIN ASSIGNMENT
nQA3 nQA4 nQB0 nQB1 QA3 QA4 QB0 QB1
24 23 22 21 20 19 18 17 VDDO nQA2 QA2 nQA1 QA1 nQA0 QA0 25 26 27 28 29 30 31 32 1
VDD
16 15 14
VDDO QB2 nQB2 QB3 nQB3 QB4 nQB4 VDDO
ICS854210
13 12 11 10 9
PCLKA
PCLKB
nPCLKB
nPCLKA
QB2 nQB2 QB3 nQB3 QB4 nQB4
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 854210CY www.icst.com/products/hiperclocks.html REV. B MAY 17, 2005
1
GND
nc
nc
PCLKB nPCLKB
QB0 nQB0 QB1 nQB1
VDDO
2
3
4
5
6
7
8
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Type Power Unused Input Input Input Input Power Power Output Output Output Output Output Output Output Output Output Output Description Core supply pin. No connect. Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential LVPECL clock input. Pulldown VDD/2 default when left floating. Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential LVPECL clock input. Pulldown VDD/2 default when left floating. Power supply ground. Output supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 5 3 4 6 7 8 9, 25, 32 10, 11 12, 13 14, 15 17, 18 19, 20 21, 22 23, 24 26, 27 28, 29 30, 31 Name VDD nc PCLKA nPCLKA PCLKB nPCLKB GN D VDDO nQB4, QB4 nQB3, QB3 nQB2, QB2 nQB1, QB1 nQB0, QB0 nQA4, QA4 nQA3, QA3 nQA2, QA2 nQA1, QA1 nQA0, QA0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVDD/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units k k
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs PCLKA or PCLKB 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nPCLKA or nPCLKB 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Outputs QA0:QA4, nQA0:nQA4, QB0:QB4 nQB0:nQB4 LOW HIGH HIGH LOW HIGH HIGH LOW LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels".
854210CY
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
4.6V -4.6V -0.5V to VDD + 0.5V 10mA 15mA -65C to 150C 47.9C/W (0 lfpm) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Negative Supply Voltage, VEE Inputs, VI Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 TBD TBD Maximum 3.465 3.465 Units V V mA mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VDD = 3.3V 5%
Symbol Parameter IIH IIL VTH VTL VPP Input High Current Input Low Current PCLKA, PCLKB nPCLKA, nPCLKB PCLKA, PCLKB nPCLKA, nPCLKB Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -10 100 -100 0.15 Minimum Typical Maximum 150 150 Units A A A A mV mV V V
Differential Input High Threshold Voltage Differential Input Low Threshold Voltage Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 1.2 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLKA, nPCLKA and PCLKB, nPCLKB is VDD + 0.3V.
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REV. B MAY 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
-40C Min Typ Max Min 25C Typ 35 0 50 1.25 50 Max Min 85C Typ Ma x
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V 5%
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change Units mV mV V mV
NOTE 1: Refer to Parameter Measurement Information, "3.3V Output Load Test Circuit" diagram.
TABLE 5. AC CHARACTERISTICS, VDD = 3.135V TO 3.465V
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time 20% to 80% 260 TBD TBD 17 5 -40C Min Typ Max 3.2 280 TBD TBD 180 Min 25C Typ Max 3.2 305 TBD TBD 190 Min 85C Typ Max 3.2 Units GHz ps ps ps ps
tPD tsk(o) tsk(pp)
tR/tF
NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
854210CY
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REV. B MAY 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD
SCOPE
Qx
Power Supply +
Float GND
-
LVDS
nQx
V
PP
Cross Points
V
CMR
GND
3.3V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx nQy Qy
tsk(o)
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
tsk(pp)
OUTPUT SKEW
VDD out
PART-TO-PART SKEW
VDD

out
DC Input
LVDS
out
DC Input
LVDS
100
VOD/ VOD out
VOS/ VOS
VOS SETUP
VOD SETUP
80% Clock Outputs
80% VOD
nPCLKA, nPCLKB PCLKA, PCLKB nQAx, nQBx QAx, QBx
20% tR tF
20%
tPD
OUTPUT RISE/FALL TIME
854210CY
PROPAGATION DELAY
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REV. B MAY 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
3.3V 3.3V LVDS_Driv er + R1 100
-
100 Ohm Differiential Transmission Line
FIGURE 2. TYPICAL LVDS DRIVER TERMINATION
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REV. B MAY 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R2 50
3.3V Zo = 50 Ohm
3.3V
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 3A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 3B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 50 R2 50 Zo = 50 Ohm C2 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 PCLK VBB nPCLK PC L K /n PC L K
R4 125
FIGURE 3C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK R4 120
3.3V 3.3V Zo = 50 Ohm LVDS R5 100 Zo = 50 Ohm R1 1K R2 1K C1 PCLK C2 VBB nPCLK PC L K /n PC L K
R1 120
R2 120
FIGURE 3E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 3F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
854210CY
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REV. B MAY 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
32L LQFP
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS854210 is: 394
854210CY
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REV. B MAY 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
32L LQFP
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
854210CY
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REV. B MAY 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS854210
LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Marking ICS854210CY ICS854210CY Package 32 lead LQFP 32 lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS854210CY ICS854210CYT
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 854210CY
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REV. B MAY 17, 2005

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